Semiconductor devices and ICs are generally contained in semiconductor packages comprising a protective coating or encapsulant to prevent damage during handling and assembly of the components during shipping and when mounting the components on printed circuit boards. For cost reasons, the encapsulant is preferably made of plastic. In a liquid state, the plastic “mold compound” is injected into a mold chamber at an elevated temperature surrounding the device and its interconnections before cooling and curing into a solid plastic. Such packages are commonly referred to as injection molded using a method known as “transfer molding”.
Interconnection to the device is performed through a metallic leadframe, generally of copper, conducting electrical current and heat from the semiconductor device or “die” into the printed circuit board and its surroundings. Connections between the die and the leadframe generally comprise conductive or insulating epoxy to mount the die onto the leadframe's “die pad”, and metallic bond wires, typically gold, copper, or aluminum, to connect the die's surface connections to the leadframe. Alternatively, solder balls, gold bumps, or copper pillars may be used to attach the topside connections of die directly onto the leadframe.
While the metallic leadframe acts as an electrical and thermal conductor in the finished product, during manufacturing the leadframe temporarily holds the device elements together until the plastic hardens. After plastic curing, the packaged die is separated or “singulated” from other packages also formed on the same leadframe by mechanical sawing or by mechanical punching. The saw or punch cuts through the metal leadframe and in some instances through the hardened plastic too.
In “leaded” semiconductor packages, i.e. packages where the metallic leads or “pins” protrude beyond the plastic, the leads are then bent using mechanical forming to set them into their final shape. In other instances the metallic contacts to the semiconductor occur through conductors only accessible on the underside of the package. Such devices are known as “leadless” packages. Regardless of leaded or leadless construction, after manufacturing, finished devices are packed into tape and reels ready for assembly onto customers' printed circuit boards (PCBs).
Leaded Packages One example of a conventional leaded package is shown in cross section in FIG. 1A, where a metallic leadframe, typically of copper, comprises at least two conductors 1A and 1B electrically isolated from one another and held together by molded plastic 6. Conductor 1A, the die pad, has semiconductor die 4 mounted on it and attached mechanically and electrically by die attach layer 10 typically comprising epoxy, conductive epoxy, or solder. Die pad comprising conductor 1A then extends outside of molded plastic 6 into a conductive lead mechanically bent to form bent portion 2A and flat portion 3A. Solder 8A, covering flat portion 3A and electrically connecting conductor 1A and semiconductor die 4 to PCB conductive trace 7A formed in PCB 9.
The surface of semiconductor die 4 includes one or more exposed metallized areas for electrical connections (not shown), electrically connected by bond wire 5 and possibly others (not shown), comprising gold, copper, aluminum or conductive metallic alloys. In this example, bond wire 5 connects a portion of semiconductor die 4 to conductor 1B. Conductor 1B extends laterally outside of molded plastic 6 and through bent portion 2B and flat portion 3B onto conductive trace 7B in PCB 9. Solder 8B electrically and mechanically connects flat portion 3B of conductor 1B to PCB conductive trace 7B.
Manufacturing of the device involves mechanically bending leads to form bent portions 2A and 2B such that the bottom of flat portions 3A and 3B are coplanar for mounting on a flat surface, i.e. PCB 9. Packages with bent leads on two or more package edges are commonly referred to as “gull wing ” packages owing to their curved lead shape. Unfortunately, mechanical processes are imperfect and subject to unavoidable variability. Attempts to scale gull wing packages to thin dimensions, i.e. to manufacture low profile gull wing packages, fail below 1mm heights because the mechanical variability becomes and intolerable percentage of the total package height. As such, gull wing packages are not able to serve the market for thin products and such packages have been completely eliminated from cell phone and tablet designs. Other products where gull wing packages persist because of their relatively low cost are, however, unable to be miniaturized in part because of the minimum height restrictions of gull wing packages.
Aside from issues with scaling gull wing packages to below 0.8 mm for low profile applications, such IC packages do not normally include a thick exposed die pad to act as a heat sink and without special design modifications are therefore unable to dissipate any significant power or spread heat effectively. Despite its limitation in profile height, poor lead coplanarity, and lack of heat sinking, one advantage of gull wing packages is their compatibility with low-cost “wave-solder” PCB assembly methods. Wave-solder based PCB manufacturing is significantly easier and cheaper than reflow assembly used in high tech PCB factories for cell phones and tablets, offering a cost advantage per PCB area of 2× to 4× over reflow assembly. In consumer electronics large PCBs such as those used in HDTV backlighting, the PCB cost per board area is a dominant economic consideration overriding concerns or the limitations in lead coplanarity, package height, and power dissipation suffered by gull wing packages.
Gull wing type packages include small outline or “SO” packages such as the eight-lead SOP8, the sixteen-lead SOP16, etc.; the three pin small outline transistor or “SOT” package such as the SOT23;the thin small outline package or TSOP package such as the six-lead TSOP6; the thin super small outline package such as the sixteen lead TSSOP16, the quad leaded flat pack such as the 24-lead QFP24, and the low-profile quad leaded flat pack such as the 28 lead LQFP. The term “low-profile” is historic as compared to other gull wing packages of the day and still requires at least a 2 mm minimum height, i.e. not low profile by today's standards for low-profile meaning package heights ranging from 0.4 mm to 0.8 mm.
FIG. 1B illustrates the cross section of another type of surface mount package unable to scale to thin dimensions. The package, known as the transistor outline or “TO” type package, is used for power packages needed for dissipating and spreading heat from a power semiconductor device or voltage regulator into a printed circuit board. Popular TO packages include the leaded TO-220 for through hole mounting and its surface mount versions, the TO-252 also known as the DPAK, and the TO-263 or D2PAK. Such power packages rely on die pad 1C with an exposed back side as a heatsink in order to achieve heat spreading, improve package power dissipation, and lower the package's thermal resistance. Also known as a heat slug, die pad 1C may include an additional heat tab 1D extending laterally from die pad 1C beyond molded plastic 6. Power semiconductor die 4 is attached to die pad 1C using die attach 10 which generally comprises conductive epoxy or solder.
Unlike the previously illustrated integrated circuit package, in power applications both current and heat are conducted out of the package from the bottom of semiconductor die 4. As such, the backside of semiconductor die 4 generally includes a backside metal such as a tri-metal sandwich of titanium, nickel and silver or gold to form a solderable backside. The tri-metal sandwich is deposited on the backside of the die during wafer fabrication after mechanical and chemical thinning and roughening of the substrate. The roughening is required both for good adherence as well as to insure good ohmic contact, i.e. low contact resistance, between the metal and the semiconductor.
As in the IC package shown in FIG. 1B, the surface of semiconductor die 4 includes one or more exposed metallized areas for electrical connections (not shown), connected electrically to conductive lead 1B by bond wire 5 and possibly others (not shown), comprising gold, copper, aluminum or conductive metallic alloys. In this example, bond wire 5 connects a portion of semiconductor die 4 to conductor 1B. Conductor 1B extends laterally outside of molded plastic 6 and through bent portion 2B and flat portion 3B onto conductive trace 7B in PCB 9. Solder 8B electrically and mechanically connects flat portion 3B of conductor 1B to PCB conductive trace 7B. Manufacturing of the device involves mechanically bending leads to form bent portion 2B and others (not shown) such that the bottom of flat portion 3B is coplanar with the exposed bottom surface of die pad 1C for mounting on a flat surface, i.e. PCB 9. Unfortunately, mechanical processes are imperfect and subject to unavoidable variability, leading to mismatches between the bottom of flat portion 3B and die pad 1C.
In PCB 9 board assembly, solder 8B, typically formed by wave-soldering easily covers package lead flat portion 3B but as shown by solder 8A is unable to cover heat tab 1D. As a result, a layer of additional solder 11 must be place atop PCB conductor 7A before mounting the power package, using wave-soldering. The operation of placing solder onto the PCB is generally performed one package at a time, using pick and place machines, or in low cost factories, manually, using low-cost factory workers. Aside from its poor coplanarity between the bottom of leads and the back of an exposed die pad and its inability to scale to thin package profiles, the need for manual placement of the solder under the heat tab is another disadvantage of conventional surface mount power packages.
FIG. 2 illustrates a flow chart of a process for manufacturing leaded surface mount packages. Both packages start with copper sheet 20. The width of the sheet is matched in width to the machines intended to handle and process the strip in assembly. The thickness of the copper is typically 200 μm for ICs and 500 μm for power packages. In the case of ICs, as indicated in step 21B, a one side masked etch is optionally performed to define the die pad, leads, as well as the leadframe rail and tie bars used to hold everything together during processing. In the case of power packages, as indicated in step 21A, the leadframe must be selectively thinned to distinguish the leads from the thick die pad. A second etch is then required to define the die pad, leads, as well as the leadframe rail and tie bars used to hold everything together during subsequent processing. As an alternative process, a punch can be used to define the die pad, leads and support, then a stamp can be used selectively to squeeze metal locally to thin it. This mechanical process, while faster than etching, creates several problems. First, compressed metal exhibits mechanical stress not present in etched leadframes. Stress can lead to cracking of plastic or silicon die contacting the stressed metal. As a further complication, in leads mechanically thinned by stamping, the excess metal squeezes out the sides of the thinned lead and must be removed by trimming.
In either case, after the leadframe is etched or mechanically formed, the leadframe is now ready for die attach 22 comprising either epoxy for ICs or conductive epoxy or solder for power packages. After die attach (step 22), wire bonding 23A is performed using gold or copper wire for ICs and using copper or aluminum wire for power packages. Alternatively, for power devices, after bonding the gate wire in step 23A, the clip lead is attached for the high current connection to the device's topside in step 23B.
In step 24, leadframe specific molding 24 is performed, meaning each leadframe requires its own customized leadframe cavity design to insure the plastic is located only around specific regions containing the semiconductor, wire bonds and portions of the leadframe, but not containing the lead extensions, tie bars and leadframe rails. After the plastic is melted to form the individual packages, deflash operation in step 25 removes excess plastic using mechanical or chemical processes. Next, to enable improved solderability and prevent oxidation of the copper leadframe, the post-molded copper leadframe is plated with tin, nickel, zinc, or palladium and then chemically etched to remove any excess plating material (step 26). Lastly the leads are bent and cut in step 27, separating each packaged die and its corresponding leads from others manufactured on the same leadframe. This final step, also referred to as singulation or trim and dejunk, results in individually packaged IC or power devices ready for electrical test. The remainder of the leadframe, including tie bars, rails, etc., is then recycled to recover the copper for future use.
One major disadvantage of leaded package technology is that each package needs its own mold, commonly requiring an initial investment of over $100,000 USD. Manufacturers must consider this initial cost when performing calculations regarding their expected financial return on investment of ROI, and the TTR, i.e. the time required for recouping their investment. The unintended consequence of high initial investment is that companies become more cautious about releasing new packages into the market, new package technology and capability become commercially available at a slower pace, and consequentially innovation and advancement slow to a snail's pace. These factors explain why power packages have progressed very little over the last five decades.
Another consideration in manufacturing is affect of UPH or units per hour throughput on unit cost. Unit cost comprises material and labor costs plus the initial investment divided by the UPH. High initial investment and low UPH both adversely contribute to product cost. While UPH for molding machines is high, productivity is sacrificed every time the factory switches packages. To change from one package to another, a mold machine must be taken out of service and the mold cavity tool, the machined steel blocks that define where the plastic goes, must be manually changed. The mold machine must be reheated, and recalibrated often with some test runs to confirm that it is working well before running any production material through it. Down time for changing the mold tool can be an hour or longer, reducing the average throughput and increasing production net cost per unit. As much as possible, factory management will choose to avoid changing the mold tool during a work shift, delaying a specific customer's production for one or more shifts, or even for days to maximize factory throughput, even at the expense of customer service.
An example of a leaded surface mount package leadframe, before and after molding, is shown in FIG. 3A. Photo 30A illustrates IC leadframe 33A prior to molding including conductive leads 33A and die pad 33B. In the example shown the lead frame comprises 22 leads on each of two sides of the plastic body thereby comprising a 44 lead, also known as a 44-pin, surface mount package. After molding, as shown in photo 30B, the die pad, semiconductor die and bond-wires are encapsulated by plastic, leaving only the exterior portion of conductive leads 33B exposed. During manufacturing, every die pad is covered by its own separately molded plastic, as defined by a mold cavity tool uniquely for the specific package type. After singulation, i.e. separating the package from the leadframe, the resulting package is shown in perspective drawings 33A and 33B. The number of conductive leads may vary considerably, with dual-sided packages having from two to seven dozen leads on each side. Common dual-side packages include 3, 4, 6, 8, 12, 16, 18, 20, 24, 28, 32, 36, 40, 44 and 48 leads in total.
FIG. 3B illustrates several examples of small outline or “SO” type packages including the ubiquitous SO-8, a small outline package with 8-leads 33E shown in perspective view 31E from above and from underneath in view 32E. As shown, package 31F has 10-leads 33F, and package-31G includes 16-leads 33F. The package shown in topside view 31D includes 20-leads 33D. The underside view 32D of the same package illustrates exposed die pad 34D used to improve thermal conduction. Guaranteeing coplanarity between exposed die pad 34D and the bottom of leads 33D in manufacturing however remains problematic. Therefore most SO type packages such as the 36-lead package shown in topside view 31C and underside view 32C do not include an exposed die pad and are not intended for power applications.
Low pin count packages such as those shown in FIG. 3C are commonly used for single transistors, dual transistors, or small analog integrated circuits such as voltage regulators, provided that the component's power dissipation is limited. Such packages may include the small outline transistor or SOT23 package 31K having three leads 33K, the thin small outline package or TSOP including a 5-lead version 33H shown in topside and underside views 31H and 32H, 6-lead version 33L shown in topside view 31L, and the improved area efficiency J-lead wide-body package known as the TSOP-JW shown in topside and underside views 31J and 32J. Leads 33J bend underneath the package to accommodate a larger package body and die area than conventional gull wing packages. While the name suggests the package lead has a J shape, the process of mechanical lead bending actually produces an inverse gull wing, essentially the same as other gull wing packages except the leads are bent under the package body instead of outside.
Higher pin count packages utilize the placement of gull wing shaped leads on all four sides of a package, and are therefore referred to as leaded quad flat packs or LQFP packages. As shown in FIG. 3D topside and underside views 31M and 32M illustrate a 32-lead LQFP having 8 gull-wing leads 33M on each side of the package while topside and underside views 31N and 32N illustrate a 48-lead LQFP having 16 gull-wing leads 33N per side. Topside and underside views 310 and 320 illustrate a LQFP with gull wing leads 330 and exposed die pad 340. As in the previous SO package description, maintaining good coplanarity between the bottom of exposed die pad 340 and leads 330 is problematic since the alignment is entirely mechanical and subject to unavoidable manufacturing variability. This variability is especially severe in low profile packages so LQFP packages with exposed die pads typically have heights of 1 mm or greater.
Another class of packages comprising bent and stamped metal leadframes are those used in transistor outline or “TO” type power packages such as the aforementioned DPAK and D2PAK as shown in top perspective views 31P and 35P and top view 31Q in FIG. 3E. The conductive leads 33P and 33Q are bent into place during manufacturing ideally to be coplanar with the bottom of heat tab 36Q. Leads 33Q as shown, vary in width being slightly wider in the middle of the lead. This extra metal is left over from tie bars used to hold the leadframe together during manufacturing. The leadframe construction of view 30R shown prior to trimming and singulation illustrates the location of tie bar 37R connected to leads 33R as well as die pad 34R and heat tab 36R. While the top view appears coplanar, the actual leadframe is mechanically stamped into a multi-planar construction shown in perspective view 30S, where die pad 34S and heat tab 36S are stamped and compressed to a height below that of leads 33S and tie bar 37S.
In contrast to the traditional DPAK and D2PAK of the prior illustration, FIG. 3F illustrates various alternative packages comprising a combination of DPAK-like heat sink design with an eight lead package similar in outline to the SOP8. In top view 38A, the power device sits atop a die pad connected to four leads 40A and where bond wires 39A connect the die's top metallization to three leads used to carry high current and to another lead for the transistor's gate or input. In top view 38B, the power device sits atop a die pad connected to four leads 40B and a bond wire connects to the gate input lead but the power-carrying bond wires have been replaced with copper clips 39B. Top views 38C and 38E illustrate alternate designs for clip leads 39C and 39E. Top view 38D illustrates the use of a large number of gold or copper wires 39D to achieve a low package resistance while eliminating the need for large diameter bond wires or clips. Finally perspective view 38F illustrates an alternate clip lead design 39F where even the gate lead is connected by a copper clip. As clearly illustrated even in clip lead designs, the copper clip comprises leads that are mechanically bent in portion 41F so that the bottom of the clip lead 40F is designed to be coplanar with the back of heat tab 42F.
In manufacturing however, maintaining coplanarity remains problematic especially in low-profile package designs. The issue of coplanarity is revealed in the SEM cross sections shown in FIG. 3G, where the back of the exposed die pad and heat tab 42F should be coplanar with flat portion 40F of lead 41F after bending. Too much bending will result in the lead 41F and its flat portion 40F extending below die pad and heat tab 42F, while too little bending has the opposite effect, causing below die pad and heat tab 42F to extend below lead 41F and its flat portion 40F. As shown solder 44F wets onto the side of lead 41F but because of the thickness of lead 40F and flat portion 41F the solder is unable to cover the lead thoroughly. As such additional solder 43F must be manually positioned onto a PCB before mounting the device in order to insure solder 43F solders lead 41F and exposed die pad and heat tab 42F to board reliably. Examples of a SOP type small power packages are shown in the photographs of FIG. 3H illustrating the underside view 45G of a package with four leads 40G not connected to the die pad and one exposed die pad 42G with a connected heat tab. Underside view 45H illustrates a design where exposed die pad 42H does not connect to a heat tab but instead connects to four additional leads other than leads 40H not connected to die pad 42H.
Lastly in FIG. 3J, and number of leaded power packages such as TO220and variants thereof are shown. While these packages are not surface mount devices in the sense that the package leads do not solder flat onto a PCB, the heat tab may be attached or surface mounted onto a heat sink for additional cooling. Top view 45J and underside view 46J illustrate one such package with two through-hole leads 40J. A similar package is shown in top perspective view 45N and underside view 46N. Top-view 45K illustrates another package with two long through-hole leads 40K and heat tab 42K. Top view 45L and underside view 46L illustrate one such package with three long through-hole leads 40L and heat tab 42L. Perspective view 45O illustrates a long lead package with seven leads 40O and heat tab 42O. Top perspective views 46P and 45O reveal a package with heat tab 42P and complex lead bending resulting in leads 40P bent into two distinct rows. Mounting of packages with two rows of bent leads 40M is shown in side perspective view of power package 45M mounted on a PCB.
Leadless Packages Another class of surface mount semiconductor package is the “leadless” or “no lead” package. Unlike leaded packages where the conductor connecting the semiconductor die to the outside world protrudes out the sides of the package's protective plastic body, in a leadless package, the conductors connected to the device or IC are available for connection to a PCB only on the underneath side of the package and not through leads protruding from the package.
Because no leads protrude from the package, leadless packages have several unique properties, some advantageous and some restrictive. Being leadless, the areal efficiency of leadless packages is significantly improved compared to leaded packages. Package area efficiency, the maximum die size divided by the external footprint, i.e. the lateral extent of the leads or plastic whichever is larger, is poor for leaded packages because a lot of space is wasted by the need to bend the lead down to the PCB surface. Package area efficiencies of 20% to 30% or worse are not uncommon for small packages like SOT and TSOP packages where significant portions of the package's area and volume are “wasted” by plastic and metal available for the semiconductor die. In contrast, leadless package can have area efficiencies in the 70% to 80% range. And because no metal extends from the sides of the leadless package, there is less risk of electrical shorts to neighboring components. As a result other components on a PCB can be put closer to a leadless package than to a leadless one, i.e. leadless packages don't require as large of keep-out zone on the PCB. The benefit of a smaller “keep-out” is a higher PCB areal efficiency, meaning it is possible to pack more semiconductor die area in the same PCB space. So leadless packages offer both better package areal efficiency and PCB areal efficiency than leaded packages.
Another benefit of leadless packages is they are intrinsically coplanar. As an artifact of its manufacturing process, the bottom of every electrical connection appearing on the underside of a leadless package are, by definition, in the same geometric plane as all the others because they constitute a common piece of copper. No lead bending is involved in forming the pins so no mechanical variability is present in forming the package's exposed conductors, also known as outer leads or “lands”.
Moreover, since the die pad is formed from the same uniformly thick common copper sheet as the exposed conductors comprising the package's electrical connections or conductive lands, the bottom of the die pad is intrinsically coplanar with all the package's connections. Consequently, the die pad of a leadless package is naturally exposed on the package's underside, i.e. not isolated from the PCB, as an unavoidable artifact of its manufacturing process. If an isolated or unexposed die pad is desired, extra-steps must be incurred in the leadless package fabrication sequence to insure plastic fully encapsulates the die pad during molding.
The upper drawing in FIG. 4 illustrates the cross section of a leadframe 50 showing multiple products being manufactured concurrently. As shown, semiconductor die 54A is attached to exposed die pad 51A using either conductive or insulating epoxy. Bond wire 55A electrically connects semiconductor die 54A to conductive land 51B, and bond wire 55B electrically connects semiconductor die 54A to conductive land 51C. The entire device including the leadframe, die, and bond wires is encapsulated in molded plastic 56. In an adjacent section of leadframe 50, semiconductor die 54B is attached to exposed die pad 51D and electrically connected to landing pad 51E by bond wire 55C and other connections (shown only in part). Separate products are defined by saw lines 59, so although conductive lands 51B and 51E, and similarly conductive lands 51C and 51F actually comprise common pieces of copper, during sawing they are separated into different products.
During singulation, sawing, or optionally mechanical punching, cuts are made through both molded plastic 56 and the copper leadframe to separate one product from its neighbors and to cut away any connection to the leadframe rails or tie bars. The resulting singulated product is shown by example in the lower drawing of FIG. 4 for the product containing semiconductor die 54A. Because sawing along line 51B cuts both copper and plastic, the lateral extent of conductive land 51B and molded plastic 56 are coincident with vertical saw line 59, forming a vertical sidewall to the leadless package. Because of its manufacturing process, no lead can protrude laterally beyond the plastic giving the package its description as “leadless”.
To mount a leadless package onto a printed circuit board, electrically connecting conductive lands 51C and 51B and exposed die pad 51A to PCB conductive traces 7, a layer of solder or solder paste 61 must be applied before placing the package onto the PCB. This means solder or solder paste 61 must be printed or screened onto the PCB in select places as part of PCB manufacturing. After the product is positioned on top of the solder paste, the PCB is run through a “reflow oven” or belt furnace to heat the solder paste past its melting point and electrically and mechanically connect the product's conductive lands 51C and 51B and exposed die pad 51A to the PCB conductive traces 7. Because, however, the solder paste must be screened onto the PCB in advance, and an expensive temperature regulated reflow oven or belt furnace is required, manufacturing cost for reflow PCB manufacturing can be twice to four times the cost of simple wave-soldering, where the PCB and components are simply dipped in solder. This higher PCB assembly cost represents one of the major disadvantages of leadless packaging.
The manufacturing process for leadless packages is illustrated in the flow chart shown in FIG. 5, where a copper sheet (step 60) is either etched or stamped (step 61) to define the leadframe's die pad, conductive lands, tie bars, and rails, then plated with a solderable metal (step 62) such as tin, nickel, etc. to inhibit oxidation of the copper. Once the lead frames are prepared, product manufacturing may commence comprising die attach (step 63), wire bonding (step 64), molding (step 65), sawing or punching for singulation (step 66), and deflash etching (step 67) to remove any plastic residue leftover from sawing or punching.
Unlike leaded packages, where each individual part requires its own predefined mold cavity to isolate the plastic around a single product, in leadless package manufacturing entire matrices or arrays of products are assembled and then molded into one common block of plastic. This process is illustrated pictorially in FIG. 6A where one common leadframe 70A prior to molding comprises the die pads and conductive lands for hundreds of distinct and separate products 71A on a single leadframe. The leadframe after molding 72A however contains only a few large blocks of molded plastic 73A, each block containing dozens of products to be separated by sawing or punching. As such different size products can be manufactured simply by changing the leadframe with no change required in the molding machine or mold cavity tools. This feature, the ability to make different sized products represents an important benefit of leadless package manufacturing and one compelling advantage explaining the broad success and ubiquity of the package today.
A variety of four sided leadless packages made using the aforementioned process are illustrated in FIG. 6B. Using a nomenclature borrowed from four-sided leaded packages, i.e. the LQFP or the leaded quad flat pack, four-sided leadless packages are referred to as quad flat no-lead packages or QFN packages. The term four-sided or quad means that electrical connections are present on all four edges of the package but are not necessarily limited to having the same number of conductive landings on each edge. For example, the QFN shown in bottom view 75B has a total of 20 conductive landings 76B comprising 6 conductive landings on two edges and four conductive landings on the other two edges. It also has an exposed die pad 77B, which may electrically be connected to one of the conductive landings.
The top perspective view 74B clearly reveals no leads are evident on the package or protruding from its sides. Only small pieces of metal, saw-cut flush with the plastic package sidewall, reveal the location of the conductive landings. While constituting a visibly identifiable feature, the exposed metal on the package vertical sidewall is not sufficient in area for soldering. Instead, electrical connection must be made underneath the package, directly to conductive landings 76B. Similarly, underside view 75C illustrates a package with 48 conductive landing pads 76C, sixteen on each edge as well as an exposed die pad 77C. The top view 74C shows no protrusions identifying the presence of conductive leads. Underside view 75D illustrates a underside view of a QFN type leadless package with an exposed die pad 77D and 40 conductive landings 76D, ten on each edge and its corresponding topside view. Another QFN package design also with 40 conductive landings 76E is shown in underside view 75E except that die pad 77E is larger than that of die pad 77D in the previous design.
Four-sided QFN leadless packages are commercially available in fixed mm increments, e.g. 2×2, 3×3, 4×4, 5×5, 6×6, etc. While the package dimensions may be standardized, there is no corresponding standardized size for the exposed die pad. For example, underside view 74F in FIG. 6C illustrates a package with 48 landing pads 76F, sixteen on each of four sides, but with an exposed die pad 77F comprising only a small fraction of the total package area and footprint. Variations in die pad design are especially evident in smaller QFN packages such as contrasted by the package with underside view 75L having a large die pad 77L with 16 conductive landings versus the package of underside view 75J having a relatively large die pad 77J with 12 conductive landings.
As shown in FIG. 6D, leadless packages are also available in selected rectangular versions, generally with low aspect ratios, e.g. 2×3, 3×5, etc. For example, a rectangular QFN shown in top perspective view 74Q and underside view 75Q comprises 38 conductive landings 76Q combining 12 conductive landings positioned along the package's long edges with 7 conductive landings located on the short edge. Exposed die pad 77Q may be electrically connected to one or more of the conductive landings or be electrically isolated, enabling the package to support 39 distinct electrical connections.
In another variation in leadless package design, conductive landings are located on only two of the package's edges instead of all four. Such packages are referred to as DFN packages, where DFN is an acronym for dual-sided flat no-lead packages. Examples include the DFN package shown in underside view 75P comprising elongated die pad 77P and six conductive landings 76P and package shown in underside view 75T also comprising 6 conductive landings 76T and an alternately shaped die pad 77T. As in the prior examples, die pad 77T may be electrically shorted to one or more of the conductive landings or may be electrically independent. In the design shown in underside perspective view 75R, a rectangular DFN comprises exposed die pad 77R with 7 conductive landings on each long edge of the package.
In the extreme, the DFN design can be adapted for as little as two conductive landings 76K as shown in the package with underside view 75K as shown in FIG. 6E. Exposed die pad 77K functions as a third electrode making the package shown in topside perspective view 74K suitable for single transistors. Another leadless package for transistors is shown in the underside view 75S comprising two conductive landings 76S and small die pad 77S.
Leadless package manufacturing for QFN and DFN packages can also support dual die designs using two separated die pads as illustrated by the rectangular package shown in FIG. 6F. For example, in topside perspective view 74G and corresponding underside view 75G, a QFN package comprises two distinct exposed die pads 77G, six evenly spaced conductive landings 76G on the package's two short edges and seven unevenly spaced conductive landings on both of its long edges. Despite its unique dual die pad design, topside perspective view 74G appears identical to a single pad package of the same dimensions. Another dual die pad package shown in above perspective view 74H and in underside view 75H has two distinct exposed die pads 77H with six conductive landings 76H, three on each of two edges. A longer aspect ratio design is illustrated by the package with underside view 75U with 8 conductive landings 76U and two separate die pads 77U. In PCB assembly care must be taken to prevent shorts between the two die pads by insuring sufficient spacing.
As illustrated in FIG. 6G, leadless packages can also be manufactured without any exposed die pad. For example the DFN package with underside view 75N comprises eight conductive landings 76N three each on opposing edges while the underside view 75O represents a package with ten conductive landings 76O. As stated previously, in the leadless fabrication sequence described, extra processing steps must be included to eliminate the exposed die pad.
Lastly in FIG. 6H, a QFN with a curved edge is illustrated where conductive landings 76M and the width of the base of the package shown in underside view 75M is larger in dimension than the top of the package shown in topside perspective view 74M. Such a package cannot be manufactured in the standard process described for QFN and DFN fabrications because sawing or punching unavoidably results in a perfectly vertical edge sidewall to the package with all the plastic and metal cut flush by the saw cutline. Instead, such a package requires a separate mold cavity tool for each unique package much like the manufacturing of leaded packages like the SOP, SOT, and DPAK. This method of manufacturing, defining the plastic location by the molding process rather than by sawing, eliminates one of the major advantages of leadless package manufacturing—the elimination of custom package-specific mold cavity tools.
Summary Leadless packages offer unique advantages in flexible package manufacturing, coplanarity, low-profile capability, and the elimination of the need for expensive package-specific mold cavity tools. For all of its advantages, one major disadvantage of the QFN/DFN leadless package is its inability to be used in wave-solder PCB factories. Because no metal lead protrudes laterally from the package, wave-soldering cannot penetrate beneath the package to solder the die pad and the conductive landings onto the PCB conductors. Instead, the solder must be screened using a mask onto the PCB before component placement. Also, solder flow must be performed in expensive reflow ovens or belt furnaces making the entire PCB assembly process 2 to 4 times more expensive than that of simple wave-solder factory based production. Moreover, visual inspection of leadless packages soldered to a PCB using simple automated camera inspection is impossible because the solder cannot be confirmed from the top view. Instead expensive X-ray inspection equipment is required, adding cost and safety risk into reflow PCB manufacturing.
In contrast, leaded packages such as the SOP and SOT offer a cost advantage in PCB assembly because they are wave-solder compatible and easily assembled onto low cost PCBs manufactured in fully depreciated PCB factories dating back to the 1950's. Nevertheless, despite its benefit in PCB manufacturing, the actual package manufacturing of leaded packages suffers from many issues including poor lead coplanarity, poor manufacturing control in the lead bending process, risk of plastic cracking during lead bending, risk of delamination between the plastic and leads, and inability to be scaled into low profile package, especially for package heights below 1 mm.
Poor coplanarity also renders leaded packages difficult to heat sink using exposed die pads because the package's bent leads do not consistently align with the bottom of the die pad or heat slug. Because of long lead dimensions required to perform clamping during lead bending, the length of the conductive leads results in poor package and PCB areal efficiencies and results in excessive lead inductance, adversely affecting switching performance especially in power applications. The mounting of power devices is especially problematic because special two-step soldering is required, first to solder the exposed die pad and heat tab to the PCB, and then to wave-solder the leads. Variability in the lead-bending process combined with natural stochastic variations in the intervening solder thickness placed beneath the die pad result in unpredictable misalignments between the bottom of the bent leads and the PCB conductor, leading to poor connections, cold solder joints, intermittent contact, and degraded reliability.
Another disadvantage of leaded packages is their manufacturing inflexibility. Several manufacturing steps required in leaded package manufacturing demand the use of dedicated machinery and hardware, including a package-specific mold cavity tool, package-specific leadframe trim-and-bending machinery, package-specific dedicated handlers, package-specific dejunk and deflash hardware, and more. While equipment can generally be converted to accommodate different packages, the resulting factory downtime to convert a line from one package to another results in lost productivity and a lower UPH, thereby increasing per unit manufacturing costs.
The following table summarizes these and other considerations when comparing existing package technologies.
Package Leaded IC Leaded Power Leadless ClassPackagePackagePackageExample LQFP, SOP, TO (DPAK, QFN, DFNPackagesTSOP, SOTD2PAK)Pkg Package Package Flexible,ManufacturingSpecificSpecificInterchangeableHeightThick Very Thick Low-Profile (>1 mm)(>2 mm)(<0.8 mm)Lead CoplanarityDifficultDifficultSuperiorPower DissipationPoorSuperiorGoodPCB FactoryWave-Solder2-PassReflowPCB CostLowModerateHighInspectionOptical CameraOptical, Some Requires X-rayX-ray
Clearly from the above, no existing package meets the combined needs of the market. Moreover, each class of surface-mount package used today requires completely different semiconductor package factories for manufacturing, forcing packaging companies to choose their markets with little chance to expand into new markets without incurring significant additional capital costs.
What is needed is a single package design and manufacturing process that is able to produce surface-mount packages flexibly for both wave-solder and reflow assembly, facilitate superior coplanarity among the die pad and conductive leads, achieve low package height, provide good thermal power dissipation, minimize package inductance, and eliminate the need for package specific equipment such as mold cavity tools and leading equipment.